Test structures and models for estimating the yield impact of dishing and/or voids

ABSTRACT

A test structure comprising a test pattern is formed on a substrate. The test pattern includes a first comb structure having a plurality of tines, and a second structure. The second structure may be a snake structure having a plurality of side walls or a second comb structure having a plurality of side walls. The tines of the first comb structure are positioned within side walls of the snake structure or second comb structure. The tines of the first comb structure are offset from a center of the side walls. Test data collected from the test structure are analyzed, to estimate product yield. The test structure may have a lower layer pattern, such that topographical variations of the lower layer pattern propagate to an upper layer pattern of the test structure.

This application claims the benefit of U.S. Provisional PatentApplication No. 60/316,317, filed Aug. 31, 2001.

FIELD OF INVENTION

This invention relates to methods for measuring and evaluating theprocess and design related statistical variations of an integratedcircuit manufacturing process in order to determine their sources andtheir effects on the yield and performance of the product.

BACKGROUND

Defects (e.g., residual extra material) can cause electricallymeasurable faults (killer defects), depending on the chip layout as wellas the layer and location of the defects. These faults are responsiblefor manufacturing-related malfunction of affected chips. So, a layer andfault sensitive defect density is important for yield enhancement and tocontrol quality of process steps and product chips. See Staper, C. H.,Rosner, R. J., Integrated Circuit Yield Management and Yield Analysis:Development and Implementation IEEE Transactions on SemiconductorManufacturing, pp. 95-102, Vol. 8, No. 2, 1995, which is incorporated byreference herein in its entirety. Also see Ipri, A. C., Sarace, J. C.Integrated Circuit Process and Design Rule Evaluation Techniques RCAReview, pp. 323-350, Volume 38, Number 3, Sep. 1977, and Buehler, M. G.Microelectronic Test Chips for VLSI Electronics VLSI ElectronicsMicrostructure Science, pp. 529-576, Vol 9, Chap.9, Academic Press,1983, both of which are incorporated by reference herein in theirentireties. Electrical test structures are used to detect faults and toidentify and localize defects.

Topography-related defects are particularly significant in the copperDamascene manufacturing method. In this manufacturing method, trenchesand holes are etched in oxide layers, barrier films (e.g., Ta or TaN)and Cu films are deposited to fill the trenches, and chemical mechanicalpolishing (CMP) is used to remove the Cu overburden. It has been foundthat the deposition rate and CMP removal rates can have strong,pattern-dependent variations. These variations result in non-uniformlayer thicknesses (i.e., topography) within the final patterns of eachchip as well as chip-to-chip across wafers and lots. Since most chipshave several layers of Cu metallization or other metallization, thesethickness variations can further accumulate in each successive layer ofprocessing resulting in complex overall topographical variations. “Extramaterial” defects are formed when residual material (e.g., Ta barriermetal) remains after any polishing step (i.e., “underpolish”). The usualcountermeasure in this situation is to increase the CMP removal rate toachieve sufficient “overpolish.” However, too much overpolish canactually remove too much of the Cu metal in a given pattern, resultingin excessive metal resistance or a “missing material” defect. Thus, thefinal process must balance these concerns to achieve a reasonable“process window,” as shown in FIG. 1. FIG. 1 shows the upper metal layerprocess window as a function of CMP removal rate. In FIG. 1, segment 102shows the region in which there are shorts due to residual materialsresulting from underpolishing. Segment 103 shows the desired processwindow. Segment 104 shows the region in which there are high resistancelines or metal opens.

Residual barrier or Cu (or other) metal “extra material” defects causeelectrical shorts. Residual barrier metal defects are difficult todetect even using optimized inline inspection. Electrical teststructures are an attractive alternative for defect detection. Metal“Comb” or “SnakeComb” structures can be used to detect the presence ofelectrical shorts. FIG. 2 shows a typical metal SnakeComb structure 200,including a snake portion 202, and two comb portions 203, 204. If anextra material defect occurs between the two halves of the comb 203,204, the resulting electrical short results in excessive leakage currentdetected during subsequent electrical test. If a missing material defectoccurs within the Snake portion 202 of the structure 200, subsequentelectrical test shows an open circuit between the two ends of the snake.

Layout patterns on underlying layers can be used to stimulatetopography-related failures in metal Combs and SnakeCombs 300 includingmetal 2 lines 302 and 303, as shown in FIGS. 3A and 3B. FIGS. 3A and 3Bshow residual metal 2 (M2) 305 shorting lines 302 of a snakecombstructure 300 as a result of dishing in the metal 1 (M1) line (lowerlayer) 301. The residual M2 metal 305 is in the M1 “dish”. The depositedoxide profile 307 and final polished oxide profile 309 are shown. Theresidual M2 metal 305 lies beneath the final polished oxide profile 309(because of the M1 dishing) and is not removed by the polishing.However, the design of the underlying patterns 301 must be carefullyconstructed in order to stimulate the desired failure modes in a mannerwhich uniquely identifies them from other possible failure modes.Furthermore, the effect of the underlying patterns 301 on the yield ofthe metal SnakeComb 300 is dependent on the design of the SnakeCombitself. Finally, the test structure should be representative of layoutpatterns typically used in product chips. This ensures that the resultsfrom analysis of the test structure will be relevant to product yield.Modern design flows can result in a huge variation of possible productlayout patterns. In view of all of these factors combined, a rigorousdesign-of-experiments (DOE) for test structures for Cu (or other metal)topography analysis are desired for product yield improvement.

SUMMARY OF THE INVENTION

One aspect of the invention is a test structure comprising a testpattern on a substrate. The test pattern comprises a snake structurehaving a plurality of wells, and a comb structure having a plurality oftines positioned within wells of the snake structure. The tines can beoffset from the center of the wells.

Another aspect of the invention is a test structure comprising a testpattern on a substrate. The test pattern comprises first and second combstructures facing each other so as to have a plurality of interlacedtines. The first comb structure has a respective well between each pairof adjacent tines thereof. The tines of the second comb structure areoffset from corresponding centers of the wells.

Another aspect of the invention is analyzing test data collected fromthe test structure having a comb and an offset snake or comb, toestimate product yield thereby.

Another aspect of the invention is a method, comprising the step ofdesigning a lower layer test pattern with a design of experiment tostimulate topographical variations, which propagate to an upper layerpattern, wherein one or more of the topographical variations cause afailure in the upper layer pattern.

Another aspect of the invention is a method, comprising the step of:designing a lower layer test pattern with a first design of experimentto stimulate topographical variations that propagate to an upper layerpattern; designing variations in the upper layer pattern with a seconddesign of experiment; and coordinating the first and second designs ofexperiment with each other.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram showing how wafer yield is affected by CMP removalrate.

FIG. 2 is a diagram of a conventional SnakeComb test structure.

FIGS. 3A (plan view) and 3B (cross sectional view) show an upper layershort circuit from residual upper layer metal caused by dishing in thelower layer metal.

FIG. 4 is a plan view of an exemplary SnakeComb test structure accordingto the present invention.

FIG. 5 is a plan view of an exemplary layout including the Comb teststructure of FIG. 4.

FIG. 6 is a histogram showing die yield under various conditions, splitW1.

FIG. 7 is a histogram showing die yield, split D1.

FIG. 8 is a histogram showing die yield, split S2.

FIG. 9 is a histogram comparing experimental yield results (left bar ineach pair) with predicted yield (right bar in each pair).

FIG. 10 is a graph of yield loss due to critical area and other reasons.

FIG. 11 is a graph showing how the density of the upper layer (M2)pattern affects yield.

FIGS. 12 and 13 are plan and cross sectional views of a sample havingvoids in the lower layer.

FIGS. 14A-14D show each step of the calculation for critical area.

FIGS. 15A and 15B show a metal dishing sample in plan and crosssectional views, respectively.

FIGS. 16A and 16B are plan and cross sectional views, respectively, of ametal erosion sample.

DETAILED DESCRIPTION

U.S. Provisional Patent Application No. 60/316,317, filed Aug. 31, 2001,is incorporated by reference herein in its entirety.

Introduction

Cu (or other material) dishing on lower metal layers is known to causeresidual barrier metal material on the next metal layer resulting inelectrical shorts. Oxide dishing and metal void formation in the lowermetal layers have also been observed to lead to electrical shorts inupper metal layers. The probability of these types of failure depends onseveral factors:

-   -   1. the probability of Cu (or other metal) dishing, oxide dishing        or Cu (or other metal) voiding in the lower metal layer    -   2. the probability of transfer of lower layer topography into        upper layer oxide topography

3. the removal rate during the final polishing step during upper metallayer formation

4. the presence of upper layer metal in close enough proximity to theresidual material defect to result in a short in the upper layer metal.

Prior art metal test structures are not sufficient to characterize thiskind of failure due to both test structure design and the DOE used for asuite of such test structures on a die. A new test structure design ispresented herein, as well as a summary of the major issues which areconsidered during DOE in order to make the results of the test structurerelevant for product yield improvement.

Test Structure Design

SnakeComb test structure designs typically use equal linewidth and linespace for all elements in the SnakeComb, as shown in FIG. 2. This forcesa correlation between the critical area and density in the upper layer.Thus, factors 3 and 4, above, are inseparable with standard SnakeCombtest structures.

To allow independent control of critical area and metal density in theSnakeComb structure, one exemplary embodiment of the invention includesan “Offset SnakeComb” test structure 400 (shown in FIG. 4) may be used.Critical area is the area occupied by pattern/structure that issusceptible to specifically defined defects. In this test structure,high critical area is achieved by placing each successive pair 403, 404of “tines” 402 (i.e., a “tine pair”) in the SnakeComb 400 at minimumspace. This is accomplished by placing the tines 402 of the combstructure within wells 406 of the snake structure, with the tines offsetfrom the center C of the wells. Herein, the term “tines” covers segments402 of the combs 401 as well as segments 402 of the snake 405. Minimumspace is the minimum space S1 allowed between tines 402 within a pair(e.g., pair 403) by the layout rules. S2 defines the distance betweentine pairs. A tine pair 403 has spacing S1; to the left of tine pair 403is a second tine pair 404. Each well 406 has first and second side walls406 a and 406 b, and a minimum space between the tines 402 and either ofthe first and second side walls of one of the wells is a minimum spaceS1 allowed between any lines for a circuit pattern on the substrate.Density is then independently controlled by varying the space between“tine pairs.” Metal density is defined as (2*L)/(S1+L+S2+L) where L isthe width of the lines. For example, in the DOE of Table 1 (below),maximum density is actually approximately 80-90%% since minimum S isapproximately 0.2 μm and L is approximately 1-1.2 μm. Elements Metal 1width Metal 1 density Metal 2 comb space Values (W1) um (D1) (S2) um 1 430% 40.08 2 10 50% 18.88 3 20 83% or 90% 4.74 4 1.92 5 0.94 6 0.2

FIG. 5 is a plan view of a second exemplary layout including two of theComb test structures 502 of FIG. 4. The test pattern 500 comprises:first and second comb structures 502 a, 502 b facing each other so as tohave a plurality of interlaced tines 503 a and 503 b, the first combstructure 502 a having a respective well 505 between each pair ofadjacent tines 503 a thereof. The tines 503 b of the second combstructure 502 b are offset from corresponding centers C of the wells505.

In FIG. 5, the density D1 of metal 1 (item 504) is given byD1=W1/(W1+S1). Table 1 provides the comb-metal dishing DOE. An exemplarytest procedure for this DOE is as follows: In a full factorial DOE,there are 54 structures.

Lower layer patterns are drawn using a similar philosophy. The lowerlayer test patterns have a design of experiment to stimulatetopographical variations, which propagate to the upper layer pattern.This allows extraction of failure rates and determination of arelationship between the failure rate and the critical area of the lowerlayer test pattern. Since the lower layer patterns are drawn solely toprovide topography for the electrically tested upper layer, they are notconnected in an electrically testable configuration (e.g., a Comb) andare simply drawn as “dummy patterns.” The design of the dummy patternsis related to the actively measured patterns above.

Although the exemplary embodiment uses dummy patterns in the lowerlayer, many different kinds of patterns could stimulate topography whichcould propagate to the upper layer and cause an electrically observableshort or open circuit. For example, Cu voids can form only in corners ofsmall metal patterns (such as text or islands). So one could build anarray of such patterns under the upper layer SnakeComb to stimulatetopography and killer shorts. Any kinds of under layer patterns whichcan cause upper layer topography may be used. One of ordinary skill inthe art will understand that the appropriate DOE corresponding to anygiven under layer patterns is based on knowledge or hypotheses of thetopography generation mechanism.

The dummy patterns may have special design features. Each dummy patternmay be specifically designed in order to stimulate a particular sort offailure. For example, to stimulate Cu and oxide dishing, long lines ofvarying width and space are used. To stimulate Cu voids, Cu lines, aswell as Cu islands and other small, corner-dominated Cu structures areused. In general, any kind of dummy pattern which can stimulatetopography in the upper layer may be used. Examples of such other dummypatterns include, but are not limited to, samples of typical productlayout patterns such SRAM cell arrays or blocks of random logic orstandard cells.

The exemplary method and device provide a suite of SnakeComb structures400 or dual offset comb test structures 500 with variable line spacingsthat allow for separation of the effects of defects in the upper layerdue to specific mechanisms, e.g., shorts, opens caused by the Cu (orother material) dishing interactions with CMP removal rate, from thepresence of similar upper layer metal defects caused by other failuremechanisms. Thus a plurality of such test structures may be formed, eachtest structure having a respectively different minimum line spacing.

FIG. 11 is a graph illustrating how the density of the upper layer (M2)pattern may affect its yield. The term “L/S” stands for line/space.Curve 1101 shows the probability of M2 CMP residue as a function of M2pattern density. This parameter is varied by changing the M1 linewidthpattern under the M2 comb. Curve 1102 shows the M2 critical area as afunction of M2 pattern density. This parameter is varied by changing theS2-spacing between minimum L/S pairs in the M2 comb. Curve 1103 showsthe M2 likely yield impact trend vs. density as M2 puddle probabilityincreases while M2 critical area decreases.

Design-of-Experiments and Data Analysis

Prior art test chips used for Cu topography analysis do not allowstraightforward disaggregation of the various possible failure modeswhich can be present in any single set of data. To facilitate this task,we consider how each failure mode is stimulated by layout design as wellas how the frequency of a defect (i.e., the “defect density”) can bemodeled in a form useful for product yield prediction. Theseconsiderations then dictate the design-of-experiments (DOE) for the teststructure layout patterns.

Another aspect of the exemplary embodiment provides a DOE system thattakes into account both the defect density and how a failure mode isaffected by the design layout.

The exemplary method comprises designing a lower layer test pattern witha first design of experiment (having dummy patterns) to stimulatetopographical variations that propagate to an upper layer pattern.Variations in the upper layer pattern have a second design ofexperiment. The first and second designs of experiment are coordinatedto interact with each other. For example, the first (lower layer) designof experiment may include providing structures that maximizeobservability of a given type of defect (e.g., M2 short) in the upperlayer pattern. The second design of experiment could then includeprovision of structures having respectively different abilities to avoidthat given type of defect. The second design of experiment may includeprovision of structures having respectively different sensitivities tothe density of that given type of defect.

In FIGS. 6-8, the term “split” is still used to identify two differentruns. When one did an experiment with n variables that was splitconventionally, it meant that another experiment is designed in whichone of the variables is different, hence the two process runs were saidto be “split”. However, DOE is a formalized methodology to doexperiments with different variable arrangements exacting maximuminformation with a minimum number of experiments. In the case of a DOEsplit as described herein, more than one variable may be changed at atime in a novel way. Therefore the one at a time variable approach isreplaced by DOE. The term “split” is used herein to identify twodifferent runs.

Note that in FIGS. 6-8, the acronyms DT, OP, TP and POR do not refer tothe exemplary SnakeComb test structures on the die, but refer to the“split” conditions used during wafer processing. These conditions may beany processing conditions that are specific to a product. These data areprovided for the purpose of showing the method of analysis, and not forthe purpose of highlighting the specific conditions DT, OP, TP and PORthat were used for this sample.

In FIGS. 6-8, die yield is defined so that a die is considered good ifall the structures in the same category are good.

FIG. 6 is a histogram showing die yield under various conditions(designated DT, OP, OP+TP, POR), “split W1.” That is, the bars labeled“4” have similar values of W1 to each other, the bars labeled “10” havesimilar values of W1 to each other, and the bars labeled “20” havesimilar values of W1 to each other. In FIG. 6, a die is considered goodif all the structures with the same width are good. Among the varioussplit conditions in FIG. 6, the OP split consistently has the bestyield; the DT and POR splits have worse yields.

FIG. 7 is a histogram showing die yield, split D1. That is, the barslabeled “30” have the same values of D1 as each other; the bars labeled“50” have the same values of D1 as each other, etc. In FIG. 7, a die isconsidered good if all the structures with the same metal 1 density aregood. Among the various split conditions in FIG. 7, the OP splitconsistently has the best yield; the DT and POR splits have worseyields.

FIG. 8 is a histogram showing die yield, split S2. That is, the barslabeled “0.2” have the same values of S2 as each other; the bars labeled“0.94” have the same values of S2 as each other, etc. In FIG. 8, a dieis considered good if all the structures with the same metal 2 combspace are good. Among the various split conditions in FIG. 8, the OPsplit has the best yield for values of S2 up to 4.74; the DT and PORsplits have worse yields for values of S2 up to 4.74. For values of S2of 18.88 and 40.08, there is little difference in yield among thevarious conditions.

Exemplary analysis results for the data of FIGS. 6-8 areas follows: Ofthe split conditions used during wafer processing, the split conditiondesignated “OP” has higher yield than other splits. No closerelationship of yield to metal 1 width is apparent. No closerelationship of yield to metal 1 density is apparent. The yield has aclose relationship to metal 2 comb space/density.

In general, the data collected from the experiment are analyzed todetermine whether there is correlation between each individual designfeature under investigation and the yield, and whether there iscorrelation between each individual split process condition and yield.

FIG. 9 is a histogram comparing experimental yield results (from FIG. 8)with predicted yield. The experimental results are indicated by the leftbar in each pair of adjacent bars. The predicted yield results from thecritical area model are indicated by the right bar in each pair ofadjacent bars. When the metal 2 density is at a median level, there is alarge difference between the observed yield and the predicted yield bythe critical area model. From critical area model, yield loss shouldmonotonically increase with higher metal 2 density. From observed yield,the yield loss has a quadratic relationship to the metal 2 density.

FIG. 10 is a graph of total yield loss, predicted yield loss due tocritical area, and inferred yield loss due to other reasons, as afunction of the density of metal 2 in the experiments described abovewith reference to FIGS. 6-9. These values are defined by the equationsbelow: $\begin{matrix}{{{Yield}\quad{loss}} = {1 - {Yield}_{observed}}} & (1) \\{{{YL}\quad{due}\quad{to}\quad{CA}} = {1 - {Yield}_{{predicated}\quad{by}\quad{CA}}}} & (2) \\{{{YL}\quad{due}\quad{to}\quad{other}\quad{reason}} = {1 - \frac{{Yield}_{observed}}{{Yield}_{{predicated}\quad{by}\quad{CA}}}}} & (3)\end{matrix}$

The following conclusions may be drawn from the exemplary yieldanalysis: The critical area model cannot explain the large yield lossfor medium metal 2 density structures shown in FIG. 10 (in the curvedesignated “YL due to other reason”); there should be another systematicyield loss mechanism. The metal 2 comb space/metal 2 density hasquadratic impact on yield loss for the examples described above withreference to FIGS. 6-9. Thus, test concept originally illustrated inFIG. 11 has been realized in silicon and demonstrates the utility of thetest structure design practices and analysis methods embodied in thisinvention.

Process Fail Rate Estimation and Product Yield Impact Estimation

New yield models are desired for the new mechanisms of metal 2 shorts.Such new models may include: a metal void model, a metal dishing model,a metal erosion model, a Cu-up model, and the like. These yield modelsare formulated as a function of design pattern attributes (e.g. criticalarea) and process fail rate quantities (e.g. defect density). The drawndesign patterns of those test structures area used to estimate thecritical area for each kind of process fail mechanism. Thus, the yieldsof a set of test structures can be used along with the drawn designpatterns for those test structures to invert the yield model functionand estimate the process fail rate quantities. The process fail ratequantities are then used in conjunction with appropriate critical areasextracted from product patterns to estimate product yield impact of theprocess fail mechanism.

Yield prediction methods are described in U.S. patent application10/202,278, filed Jul. 24, 2002, and Ciplickas, Dennis et al.,“Predictive Yield Modeling of VLSIC's”, IEEE International Workshop onStatistical Metrology, Honolulu, Hi., Jun. 2000, both of which areexpressly incorporated by reference herein.

Yield impact predictions are calculated by combining the processdefectivity rates (D0, p, λ, etc.) with critical areas calculated fromproduct chip layouts. This section describes this analysis flow.

The overall model is formed by building yield predictions of individualcircuit blocks broken down by each processing layer. For example, if achip contains random logic with an SRAM core and is manufactured in atwo level metal process, the yield impact matrix shown in Table 2 isformed. Each cell of the matrix contains a yield impact prediction forthe given chip block and processing layer. The last row and column ofthe matrix contain the product of all cells in that column or row. Forexample, the product of the 10 upper left most cells (first 5 columnsand first 2 rows) evaluates to the total chip yield across all layers.TABLE 2 Total pdy contact metal 1 via metal 2 Layers Logic SRAM TotalChip

Individual yield predictions are calculated using the average failurerate of the layout in a given block and layer. The average failure rate,λ, is a well established parameter used to modeling the yield impact ofrandom defects. For example, given a block failure rate λa associatedwith a certain defect type a, a Poisson distribution can be used toestimate the fraction of chips which are not affected by the defect:Y _(a) =e ^(−λa)   (4)is known as the limited yield for defect type a. Other distributions,such as the Negative Binomial distribution, can also be used to estimatelimited yields. These other distributions are most appropriate when thefailures modeled by λa exhibit some degree of clustering. For bothclarify and brevity, however, the Poisson distribution is used toillustrate the concepts and clustered yield models are not discussedhere. Failure rates for planar interconnect layers of layout blocks canbe calculated using a traditional critical area: $\begin{matrix}{\lambda_{b,l} = {\int_{x_{0}}^{\infty}{\left\lbrack {{CA}_{e,l}(x)} \right\rbrack\left\lbrack {{{DSD}_{l}(x)}{\mathbb{d}x}} \right\rbrack}}} & (5)\end{matrix}$

-   -   where b=layout block    -   l=process block    -   x₀=minimum feature size in technology    -   x=defect size    -   CA_(b,l)(x)=critical area of block b in layer l for defect size        x    -   DSD_(l)(r)=deensity of defects in layer l with size x

Failure rates of the via hole layers in layout blocks are calculatedusing the single via or contact failure rate and the number of contactsor vias in the block:Y _(b,l) _(via) =e ^(−λ) ^(lvia) ^(N) ^(bvia)   (6)

The use of generalized failure rates per layer and block allows theyield impact matrix to model a variety of situations. The breakdown ofembedded SRAM vs. random logic shown in table 2 is a non-limitingexample of one typical configuration. If multiple, independently testedblocks are present in a design, it is recommended to break the yieldimpact matrix into rows corresponding to each block. Similarly, eventhough the above examples illustrate how to build yield impact matricesfrom classical process fail rate quantities (D0, p, λ), the methodologyallows for other process fail rate quantities to be used (e.g., Dv(x),PL(m2s,m1w), and PL(d1,d2,x)). Product yield models based on theseprocess fail rates would form new columns in the yield impact matrix.

FIGS. 12 and 13 are plan and cross sectional views, respectively, of asample having voids in the lower layer. The yield loss mechanism may bedescribed as follows. The void in metal 1 causes the metal 2 comb short.The model can be similar to the critical area short model, except the M2defects are induced by the voids in M1. Thus, the M2 defect density isactually the M1 “void density.” The pertinent M2 layout parameter isCA(x), where CA is the critical area, and x is the radius of the void.The pertinent process parameter is M1 void size distribution Dv(x).These parameters are related by the following equation:Yield=e ^(−∫CA(x)*Dv(x)dx)   (7)

-   -   Layout extraction is given by: CA(x)=(((&(m2>x))&(m1<x)), where:    -   A&B is the boolean “AND” of layers A and B;    -   !A is the boolean “NOT” or “inverse” of layer A; and    -   L>x oversizes layer L by amount x;    -   L<x undersizes layer L by amount x;    -   (&L) is the layer formed by the overlapping polygon regions in        layer L.

The process parameter Dv(x) is estimated by solving equation (7) givenYield and CA(x) for a set of test structures designed according to a DOEwith philosophy described earlier. Given CA(x) extracted from a productlayout, Dv(x) and equation (4) can be used to estimate product yield dueto the failure mechanism modeled by this critical area and measured bythe given test structure yields.

FIGS. 14A-14D show each step of the calculation for critical area. Theformula is given above. FIG. 14A is the original layout. In FIG. 14B,(m2>x) oversize m2 by x.

FIG. 14C, shows ((&(m2>x)) and (m1<x). Finally, FIG. 14D, shows the ANDof (((&(m2>x)) with (m1<x))resulting in a final polygon with area CA(x).

Although the exemplary method and device is described with reference tocopper dishing problems, the invention may be practiced to investigateother metals like tungsten that are used with the CMP process. Theinvention may be practiced with any metal in combination with any oxideinvolved in a chemical mechanical planarization process (CMP). In somedesigns, copper may not be adequate for smaller dimensions because thedimensions approach the mean free path of electrons. Also very low kdielectrics other than the present oxides may also be needed inparticular designs. One of ordinary skill can readily optimize thestructures and techniques described herein to take into account thedifferences in the materials properties.

FIGS. 15A and 15B show a metal dishing sample in plan and crosssectional views, respectively. The yield loss mechanism for metaldishing is as follows: CMP causes dishing of the wide metal 1 lines,then metal 2 comb will short. An exemplary model is as follows.

The pertinent layout parameter is: CL(m2s, m1w) is defined as thecritical length, the length of the metal 2 with a space of m2s on metal1 lines of width of m1w.

The pertinent process parameter is: PL(m2s,m1w), defined as theprobability of shorting in M2 patterns forming the critical lengthCL(m2s,m1w).

The yield equation for metal dishing is given by:Yield=e ^(−17 CL(m2s,m1w)*PL(m2s,m1w)dm2sdm1w)   (8)

Layout extraction is performed as follows:

-   -   CL(m2s,m1w)=Length(m2s,m1w)=Length(m2s,m1w)    -   Length(m2s,m1w)←SW(m2&((!(!(m1<0.5*m1w))>0.5*m1w)), where:

A*B is the boolean “OR” of layers A and B.

SW(L) is the spacing distribution of layer L

The process parameter PL(m2s,m1w) is estimated by solving equation (5)given Yield and CL(m2s,m1w) for a set of test structures designedaccording to a DOE with philosophy described earlier. Given CL(m2s,m1w)extracted from a product layout, PL(m2s,m1w) and equation (5) can beused to estimate product yield due to the failure mechanism modeled bythis critical length and measured by the given test structure yields.

FIGS. 16A and 16B are plan and cross sectional views, respectively, of ametal erosion sample. The defect mechanism is that the erosion of metal1 causes the metal 2 comb to short.

Layout parameters: CL(d1,d2,x) is defined as the critical length, thelength of the metal 2 with space of x within regions with metal 1density d1 and metal 2 density d2.

Process parameters: PL(d1,d2,x) is defined as probability of shortingfor that critical length.

The yield is defined by the equation:Yield=e ^(−∫CL(d1,d2,x)*PL(d1,d2,x)dd1dd2dx)   (9)

The process parameter PL(d1,d2,x) is estimated by solving equation (6)given Yield and CL(d1,d2,x) for a set of test structures designedaccording to a DOE with philosophy described earlier. Given CL(d1,d2,x)extracted from a product layout, PL(d1,d2,x) and equation (6) can beused to estimate product yield due to the failure mechanism modeled bythis critical length and measured by the given test structure yields.

The exemplary embodiment uses patterns related to interconnect lines todiscriminate between particles and CMP defects. Therefore higherconductivity metals appear to be most relevant for use in structuresaccording to the invention. Refractory metals like tungsten are used invia fabrication (contacts). But other high conductivity metals forinterconnect lines (e.g., aluminum) may be used.

The algorithm applies to any damascene processing method, such asW-damascene, which are used for contacts (or AlCu damascene).

Although the invention has been described in terms of exemplaryembodiments, it is not limited thereto. Rather, the appended claimsshould be construed broadly, to include other variants and embodimentsof the invention, which may be made by those skilled in the art withoutdeparting from the scope and range of equivalents of the invention.

1. A test structure comprising a test pattern on a substrate, the testpattern comprising: a snake structure having a plurality of wells, and acomb structure having a plurality of tines positioned within wells ofthe snake structure, wherein the tines are offset from a center of thewells.
 2. The test structure of claim 1, wherein each well has first andsecond side walls, and a minimum space between the tines and either ofthe first and second side walls of one of the wells is a minimum spaceallowed between any lines for a circuit pattern on the substrate.
 3. Aset of test structures, each comprising a test pattern on a substrate,the test pattern comprising: a snake structure having a plurality ofwells, and a comb structure having a plurality of tines positionedwithin wells of the snake structure, wherein the tines are offset from acenter of the wells, and each test pattern has a respectively differentmaximum distance between a side wall of one of the wells thereof and thetine of the comb structure within the one well.
 4. A test structurecomprising a test pattern on a substrate, the test pattern comprising:first and second comb structures facing each other so as to have aplurality of interlaced tines, the first comb structure having arespective well between each pair of adjacent tines thereof; wherein thetines of the second comb structure are offset from corresponding centersof the wells.
 5. The test structure of claim 6, wherein a minimum spacebetween one of the tines of the second comb structure a nearest tine ofthe first comb structure is a minimum space allowed between any linesfor a circuit pattern on the substrate.
 6. A method for analyzing testdata, comprising the steps of: forming a test structure comprising atest pattern on a substrate, the test pattern comprising: a first combstructure having a plurality of tines, and a snake structure or a secondcomb structure having a plurality of side walls, the tines of the firstcomb structure being positioned within side walls of the snake structureor second comb structure, wherein the tines of the first comb structureare offset from a center of the side walls; and analyzing test datacollected from the test structure, to estimate product yield thereby. 7.A method, comprising the step of: designing a lower layer test patternwith a design of experiment to stimulate topographical variations thatpropagate to an upper layer pattern, wherein one or more of thetopographical variations cause a failure in the upper layer pattern. 8.The method of claim 7, further comprising extracting a failure rate anddetermining a relationship between the failure rate and a critical areaof the lower and upper layer test patterns.
 9. The method of claim 7,wherein the upper layer pattern includes: a snake structure having aplurality of wells, and a comb structure having a plurality of tinespositioned within wells of the snake structure, wherein the tines areoffset from a center of the wells.
 10. A method, comprising the step of:designing a lower layer test pattern with a first design of experimentto stimulate topographical variations that propagate to an upper layerpattern; designing variations in the upper layer pattern with a seconddesign of experiment; and coordinating the first and second designs ofexperiment with each other.
 11. The method of claim 10, wherein thefirst design of experiment includes providing structures that maximizeobservability of a given type of defect in the upper layer pattern. 12.The method of claim 11, wherein the second design of experiment includesproviding structures having respectively different abilities to avoidthe given type of defect.
 13. The method of claim 11, wherein the seconddesign of experiment includes providing structures having respectivelydifferent sensitivities to a density of the given type of defect. 14.The test structure of claim 1, wherein the test structure has a lowerlayer pattern, such that topographical variations of the lower layerpattern propagate to an upper layer pattern of the test structure,wherein one or more of the topographical variations cause a failure inthe upper layer pattern.
 15. The test structure of claim 14, wherein thesnake structure and the comb structure are in the upper layer pattern.